Present-day and presently proposed fiber optics systems transmit information in the form of binary data streams from a sender through an optical fiber transission channel to a receiver at data rates or frequencies of the order to gigabits (10.sup.9 bits) per second as projected by circuit simulation techniques. A data stream is a sequence of pulses, each of the pulses being developed by the sender within a separate preassigned time slot, and the amplitude or height of each such pulse typically representing a separate piece of information--typically a "bit" (binary digit) of data, in binary logic. Each such bit accordingly is valid only within the separate corresponding time slot. For orderly synchronous transmission, each such time slot has a duration equal to a period or cycle of a clock control timer (typically a clock pulse sequence).
In such systems, frequency divider circuits (i.e., circuits for reducing by an integral factor the frequency of electrical clock pulses) are particularly useful for supplying electrical timing control required for multiplexing (or demultiplexing) the data streams supplied to (or by) the optical fiber. By "multiplexing" is typically meant, for example, the process of delivering into a single common transmission channel during separate time slots the data coming from a multiplicity, say n, of separate individual channels; so that, for example, in binary digital transmission the single common channel propagates in sequence, say one piece or bit of data from the first individual channel, followed by one bit from the second individual channel, . . . , followed by one bit from the n'th individual channel, followed by one new bit from the first individual channel, etc. (i.e., repeating the cycle of one bit in succession from each individual channel). The result is thus n-fold multiplexing of data into the common channel from the individual channels. Such multiplexing is known as "time division multiplexing," and can also be used in conjunction with sampled analog transmission, as known in the art (but will not be discussed further, only for the sake of simplicity). By "demultiplexing" is meant the opposite process, that is, of sequentially delivering the data propagating in the common channel into the multiplicity of n channels; so that, for example, the first bit in the common channel is delivered to the first channel, the second bit is delivered to the second channel, . . . , the n'th bit is delivered to the n'th channel, the (n+1)'th bit is delivered to the first channel, etc. The result here is thus n-fold demultiplexing of data from the common channel into the individual channels. Typically, multiplexing is performed at the sender, while demultiplexing is performed at the receiver, and the data propagates in the common channel from sender to receiver.
FIG. 1 shows a prior art circuit arrangement for multiplexing at a sender, for example, a multiplicity n of different data bit streams--each stream propagating in a separate one of a multiplicity n of separate individual incoming channels Ch1, Ch2, . . . Chn--into a single common outgoing channel Ch0. Assume for definiteness that the bit rate in each of the individual incoming channels Ch 1, Ch2, . . . Chn is given by f/n bits per second, and hence that the bit rate in the common channel Ch0 is f bits per second. To accomplish the desired multiplexing, each stage of an n-stage serial shift register (i.e., n successive clocked latches which impart delays D1, D2, . . . Dn, respectively, to data circulating in the register) has its timing for reception and delivery of data controlled by the same clock pulse sequence .phi.. Each stage imparts the same delay D=D1=D2= . . . Dn to the data circulating through the register synchronously with the flow of data in the channel Ch0, i.e., such that D=1/f. The register is arranged and operated as a "ring counter", that is, with the n'th (last) stage of the register connected for feeding back its output as input to the first stage of the register, each stage being initialized as described below. Typically, each stage of the serial register is a master-slave latch controlled by a two-phase clock control timing pulse sequence .phi. having a period T=1/f, for controlling the timing of reception and delivery of new data to and from each stage. Thus, the delay D of each stage is equal to the period T of the sequence .phi., as known in the art. During operation, the register must be properly initialized, i.e., by setting one and only one of the stages with a one bit and resetting every other stage with a zero bit. As time progresses during operation, the one bit moves from its original position through the shift register to the last (n'th) stage, then (through a feedback line F) to the first stage, and then again through the register to the last stage, etc., whereby during any single clock period (cycle) every stage of the register contains a zero bit except for a single stage that contains the one bit. By the time the single one bit thus circulates through the register back to its original position, say the i'th stage, the i'th channel Chi presents its next new bit of data. Each of an array of n separate input transmission gates in the form of pass transistors T1, T2, . . . Tn (each typically an enhancement mode MOS transistor) is connected for sensing at its input control (gate) terminal the bit which is instantaneously the content and hence output of a separate one of the shift register stages, and each transmission gate is further connected for delivering the data bit in the corresponding incoming channel to the common channel Ch0. Thereby, the shift register supplies control timing for turning on and off each transmission gate, whereby each transmission gate is turned on by a one bit and off by a zero bit supplied by and delivered from the corresponding shift register stage, and thus each transmission gate delivers the instantaneous data bit in the corresponding channel Ch1 . . . Chn to the common channel Ch0 in response to the one bit. Thus, since only a single one bit circulates in the entire register, only one transmission gate can be on at a time, so that only one data bit is delivered to the common channel Ch0 at a time, that is, a data bit from the individual one of the channels Ch1, Ch2, . . . Chn which is connected to that one of the input pass transistors T1, T2, . . . Tn, which is on.
Accordingly, as the single one bit successively shifts from one stage to the next through the n stages of the shift register, the pass transistors T1, T2, . . . Tn are successively turned on, one after the other, whereby the data coming in on the channels Ch1, Ch2, . . . Chn is transmitted (multiplexed) onto the common outgoing channel Ch0 in a succession of a bit of data from one channel after another, as is desired in the case of multiplexing the channels Ch1, Ch2, . . . Chn onto the channel Ch0. The multiplexer arrangment shown in FIG. 1 is also known as a "parallel-to-serial" converter, since it converts n parallel input data streams propagating from the channels Ch1, Ch2, . . . Chn into a single stream propagating in the common channel Ch0. In this common channel, one bit of data from each of the n streams thus flows serially after the other. Note that the resulting data stream flowing in the channel Ch0 automatically has a bit rate equal to f, that is, a bit rate equal to n times the bit rate (f/n) of each of the data streams flowing in the individual channels Ch1, Ch2, . . . Chn. Note also that the frequency at which the single one bit reappears in any given stage of the shift register is equal to f/n=f.div.n,, and thus the n-stage shift register connected and operated as a ring counter performs a frequency division of the clock pulse sequence .phi., the frequency of the sequence .phi.being equal to 1/T=f.
After transmitting the multiplexed signal in the transmission channel Ch0 from sender to receiver, demultiplexing (serial-to-parallel conversion) of the incoming multiplexed channel Ch0 at the receiver into (demultiplexed) channels Ch1, Ch2, . . . Chn can be performed (FIG. 2) in accordance with prior art by delivering the data from the multiplexed incoming channel Ch0 through a multiplicity n of separate Sample and Hold circuits (S&H)1, (S&H)2, . . . (S&H)n. Each of these Sample and Hold circuits has a separate sampling transmission gate T1, T2, . . . Tn which is controlled by a separate bit from an n-bit serial shift register to which the counting stream is delivered as input. The Sample function of each Sample and Hold circuit is activated by a one bit; the Hold function, by a zero bit. Input pass transistors T1, T2, . . . Tn of the Sample and Hold circuits (S&H)1, (S&H)2, . . . (S&H)n in the demultiplexing scheme shown in FIG. 2 are controlled as to their respective timing (on versus off) by a serial shift register in the same manner as the input pass transistors T1, T2, . . . Tn in the multiplexing circuit shown in FIG. 1, that is, by a (properly initialized) ring counter of n stages, whereby the channel Ch0 is demultiplexed (serial-to-parallel) onto the individual chanenls Ch1, Ch2, . . . Chn.
Note that the use in the n-fold demultiplexer of pass transistors clocked by an n-bit counting stream is preferred over the use of edge-triggered flip-flops clocked by a square wave propagating along a delay line because of the undesirable added gate delays in the response of the flip-flops ("set-up time" delay for edge-triggered latches).
Not also that each of the n-stage shift registers connected and operated as ring counters in FIGS. 1 and 2 supplies to each stage of each register a periodic data stream, each period having a total of n bits characterized by a single one bit and (n-1) zero bits. The time between arrivals at any given stage of successive one bits (in consecutive periods) is thus nT, and the frequency of such arrivals of successive one bits is thus f/n=f.div.n. Accordingly, the ring counters operate as frequency dividers. In particular, each n-stage register as a ring counter supplies a data stream of bits at the input end of the respective first stage (same as output end of last stage) thereof which is a periodic sequence having a period of n bits in length, each period having a time duration equal to nT and being composed of a single one bit followed by a succession of (n-1) zero bits. Thus, as shown in FIG. 3, equivalent operation can be achieved without the feedback: the feedback can thus be removed--i.e., the output of the last (n'th) stage of the shift register is not fed back to the first stage but is delivered only to the gate terminal of the n'th transmission gate Tn--and, instead of the feedback, the input stage of the n-stage shift register can be supplied with an input periodic stream of bits also having a period of n bits, in length (nT in time), each such period also being composed of a single one bit followed by a succession of (n-1) zero bits. This periodic data stream can thus be represented symbolically as the stream [1000 . . . 0001000 . . . 0001000 . . . ]. Here, each of the triple dots represents a sequence of consecutive zeros in sufficient number (n-7) to make the distance between successive one bits equal to the period n. Thus, this particular stream also has a period between successive one bits equal to n measured in bits (nT measured in time). Such a periodic bit stream can be viewed (upon Fourier analysis, for example) as a frequency divided sequence having a repetition rate or frequency equal to 1/n ("divide by n"), which can also be denoted as a periodic counting-bit stream of periodicity n ("modulo n") or simply as an n-bit countinggn stream. The n-bit counting stream (of periodicity n) is thus equivalent to a frequency division by n. In general, such an n-bit counting stream can be any periodic binary (i.e., two-level) digital signal, each period having a plurality of time slots n in number, the signal carried by one of such time slots in each period being of one level, and the signal carried by the other (n-1) slots in each period being of the other level. Thus, in addition to the n-bit counting stream [1000 . . . 0001000 . . . 0001000 . . . ], where each period of n bits in length consists of a single one (high level) bit followed by (n-1) zero (low level) bits, we have (by inversion) the inverted (i.e., complementary) n-bit counting stream [0111 . . . 1110111 . . . 1110111 . . . ], where each period of n bits consists of a single zero bit followed by (n-1) one bits. Both such periodic streams will be referred to simply as counting streams. In either case, however, it is important for the counting stream to be synchronous with the clock .phi.--that is, for successive bits in the counting stream to be valid at the shift register during successive time slots corresponding to (portions of) successive periods of the clock .phi. when the register can accept successive new data. Thus, the process of multiplexing (or demultiplexing) for n channels requires a counting stream of periodicity n as input to an n-stage shift register each of whose stages controls the timing (on versus off) of a separate transmission gate or switching element, such as a transistor (or a Sample and Hold Circuit), connected between a common channel and a separate individual channel.
A problem with the n-stage shift registers arranged with feedback as a ring counter (FIGS. 1-2) is that--in addition to the requirement for initializing the register by setting a single stage with a one bit and resetting every other stage with a zero bit--the register should be repeatedly re-initialized, owing to the random errors or false bits, which can arise and thereafter continually circulate in the ring counter during operation. That is, whenever an error occurs in the register, the need arises to correct the error, as by again setting (with a one bit) a single stage and resetting (with a zero bit) every other stage; otherwise, the error would undesirably persist. Thus, after a false bit occurs in a ring counter but before re-initializing, the counter will supply false control signals to the input pass transistors T1, T2, . . . Tn, whereby false multiplexing (or demultiplexing) undesirably occurs. Moreover, detection of the occurrence of false bits in, and re-initialization of, the counter would require undesirable extra circuitry and hence added cost.
Likewise, in a ring counter having an inverter in the feedback loop--called a "switchtail" or Johnson counter--during proper operation the n shift registers in the counter should attain (in sequence) only 2n different states out of the possible 2.sup.n different states attainable by n shift registers, a state being defined as a specific configuration of 0's and 1's in the registers. During operation, therefore, 2n states are "proper", whereas the remaining (2.sup.n -2n) states are "improper". If such a counter were intialized or were otherwise put in any one of the (2.sup.n -2n) improper states during operation, the counter would never get back (unless a felicitous further error occurs) into any one of the 2n proper states. Thus, if through error during operation such a counter attains any of the (2.sup.n -2n) improper states, such error must be detected and the counter must be re-initialized--all of which would require undesirable extra circuitry.
In prior art, a frequency dividing circuit which is self-initializing (self-correcting) to avoid the need for such extra circuitry has been furnished by the arrangement shown in FIG. 4. Here, an n-stage shift register is formed by a succession of shift register stages formed by a succession of master-slave (.phi..sub.1 .phi..sub.2) clocked latches 31, 32, 33, 34, . . . 3n, each controlled by first and second phase clock pulse sequences .phi..sub.1 and .phi..sub.2. Each such latch thereby forms a separate stage for imposing an (equal) associated delay D1=D2= . . . =Dn(=D) upon the signal propagating from left to right, the output of each such stage being fed back through a separate feedback line, F1, F2, F3, F4, . . . Fn, as input to an n-input NOR gate 41. Thereby, the output--divide by (n+1) or.div.(n+1)--of the arrangement is delivered to an ouput terminal 45 in the form of a counting stream of periodicity (n+1)--i.e., a periodic bit stream in which each period of bits consists of a single one bit followed by n zero bits. Note that the latches in all stages again are all clocked by the same master-slave control timing sequence (.phi..sub.1 .phi..sub.2) having a periodicity again equal to T, as known in the art, so that the successive time slots of successive bits in the bit stream are also spaced in time by the period T of the sequence (.phi..sub.1 .phi..sub.2). The NOR gate 41 operates to deliver a zero bit to the first register stage 31 during every cycle of the clock unless and until all inputs to the NOR gate 41 are zero--i.e., unless and until every stage stores a zero bit. Thus, when and only when every stage finally stores a zero, the NOR gate 41 finally delivers a one bit. In this way, the output terminal 45 then delivers the desired output sequence in the form of a succession of n zero bits followed by a single one bit, and thereafter likewise another succession of n zero bits followed by a single one bit, etc. Note that if at any time an error in the form of a spurious one (or zero) bit is developed in any stage of the register, nevertheless, after at most n cycles of the clock the error will have been corrected by the NOR gate 41 and the desired output sequence will have resumed. A multiple input NOR gate, i.e., the n-input NOR gate 41, however, requires in NMOS technology, for example, an array of n similar N-channel transistors mutually connected in parallel, and such an array for n greater than 2 or 3 causes undesirably slow operation due to the undesirably high parasitic capacitance and hence parasitic RC delay produced by the required n similar transistors in parallel (i.e., about n times the delay of each transistor). In PMOS and CMOS technologies, the multiple input NOR gate requires a chain of n similar P-channel transistors connected in series, and such an array for n greater than 2 or 3 also causes slow operation due to the undesirably high RC parasitics in such a chain.
It should be noted that the NOR gate 41 can be replaced with a multiple input NAND gate, in which case the resulting circulating counting stream will be the complement (inverse) of that circulating in the arrangement shown in FIG. 4.
In U. S. Pat. No. 3,609,391, issued to I. Hatano et al on Sept. 28, 1971 entitled "Timing Pulse Generator," a self-correcting frequency divider circuit is disclosed. However, in addition to requiring (slower) triple-input NOR gates, the circuit also requires AND gates that fan out, that is, AND gates each of whose outputs is required to drive a plurality of (to wit, four) shift register stages. Thus, means for amplifying (boosting) each of the outputs of the AND gates is needed, whereby undesirably further slower operation results. Therefore, it would be desirable to have a self-correcting frequency divider circuit that avoids these shortcomings of the prior art.